module zl_2346_5_1(ud,ld,cp,clr,d,Q,CO);
input [3:0] d;
input ud,ld,cp,clr;
output reg[3:0] Q;
output CO;

assign CO = (clr & ~ud & Q == 4'd0)|(ud & Q == 4'd9); //进位信号
always@ (posedge cp,negedge clr)
	if(~clr)//清零信号，为低电平时清零
		Q<=4'd0;
	else if(ld)//录入	
		Q<=d;
		
	else if(ud)//升
	begin
		if(Q==4'd9) Q<=4'd0;
		else Q<=Q+4'd1;
	end
		else if(~ud)//降

	begin
		if(Q==4'd0) Q<=4'd9;		
		else Q<=Q-4'd1;
	end

endmodule